Resistive based memory devices (ReRAMs), such as magnetic random access memory (MRAM), phase changeable random access memory (PRAM), resistance random access memory (RRAM), etc. can store data by programming the resistance of cells included therein. For example, an MRAM can store a logical data value of “zero” by programming a data cell to have a relatively low resistance or can store a logical data value of “one” by programming the data cell to have a relatively high resistance as shown in FIG. 1.
As further shown in FIG. 1, the resistance values provided by the different values stored therein can be distributed over a range so that different memory cells exhibit different levels of resistance even though those different memory cells are programmed with the same logical data values.
When the data is read from the data cell, the programmed value can be determined by essentially comparing the programmed resistance to a reference resistance. The programmed resistance and reference resistance can actually be provided by respective currents (i.e., currents that correspond to the logical data value stored in the cell as well as the reference). Accordingly, when the data cell is read, circuitry in the MRAM can determine the level of resistance provided by the data cell being read, based on the current, to output the logical data value stored therein. MRAMs are further discussed in, for example, Durlam et al. “A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects” 2002 Symposium on VLSI Circuits Digest of Technical Papers 158-161 (2002). MRAMs are also discussed in, for example, Debrosse et al. “A High-Speed 128-kb MRAM Core for Future Universal Memory Applications” IEEE Journal of Solid-State Circuits 39(4):678-683 (2004).
One conventional way of determining the logical data values stored in an MRAM is discussed, for example, in U.S. Pat. No. 6,982,908 to Cho. The approach discussed in Cho uses reference cells that are programmed to store both a logical data value of zero and a logical data value of one. These reference cells are placed in parallel with one another so that a current provided by the combination (i.e., the reference current) should ideally have a value that is the midpoint between a current corresponding to a logical data value of one and a current corresponding to a logical data value of zero, as shown, for example, in FIG. 2. For example, as shown in FIG. 2 of Cho, each of the wordlines includes a pair of reference cells where one of the pair is programmed with a logical data value of one, whereas the other reference cell in the pair is programmed with a logical data value of zero so that the combination of the two can provide a midpoint therebetween as a reference.
One of the drawbacks associated with this type of approach is that the actual current generated by reading the data cell (and the reference cell) can vary based on a bias voltage provided thereto, as shown in FIG. 3. The Cho patent cited above also discussed an approach to reduce the effects of biasing by including two reference cells for each wordline activated for read operations, as shown, for example, in FIG. 3 of Cho.
FIG. 4 is a conventional sense amplifier circuit (S/A) that can be used to determine data values stored in the MRAM cells using reference currents. In particular, a parallel arrangement of reference cells can be programmed so that half of the cells store a logical data value of zero whereas the remaining half store a logical data value of one to provide a reference current Iref that should ideally be at a midpoint between the currents associated with different logical data values, as shown in FIG. 5.
According to FIGS. 4 and 5, when a data cell is accessed, a current Icell is provided to a first input of the sense amplifier, whereas the reference current Iref is provided to the second input of the sense amplifier. The sense amplifier compares the voltages developed in response to the respective currents and produces a difference at the output thereof based essentially on the comparison between the reference current and the current actually provided by accessing the particular memory cell. As shown in FIG. 5, the currents provided by the data cells (and the currents provided by the reference cells) can be spread over respective ranges.